// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:14 UTC 2022
//////////////////////////////////////////////////////////////////////////////
//
//  pcs_raw_lane_pma_xface.v
//
//  Interface logic... overrides, loopbacks, etc.
//
//  Naming convention on input signals...
//  - * is the PMA signal
//  - *_r is the register override value
//  - *_i is the signal connected to the PHY core logic
//
//  Original Author: Ameer Youssef
//  Current Owner:   Ameer Youssef
//
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2013 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
//////////////////////////////////////////////////////////////////////////////
//
//    Perforce Information
//    $Author: spagnuol $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/pcs_raw_lane_pma_xface.v $
//    $DateTime: 2015/12/23 20:05:32 $
//    $Revision: #21 $
//
//////////////////////////////////////////////////////////////////////////////

`include "dwc_e12mp_phy_x4_ns_cr_macros.v"

`timescale 1ns/10fs
module dwc_e12mp_phy_x4_ns_pcs_raw_lane_pma_xface (
// -----------------------------------------------
// PMA INTERFACES
// -----------------------------------------------

// Internal from other Raw PCS lanes (pcs_raw_lane)
input  wire          lane_mplla_en_in,
input  wire          lane_mpllb_en_in,
input  wire          lane_rtune_req_in,
output wire          lane_mplla_en_out,
output wire          lane_mpllb_en_out,
output wire          lane_rtune_req_out,

// SUP interface
input  wire          mplla_en,
input  wire          mpllb_en,
input  wire          mplla_state,
input  wire          mpllb_state,
input  wire          rtune_ack,

// MPLLA clocks
input  wire          mplla_word_clk,
input  wire          mplla_dword_clk,
input  wire          mplla_qword_clk,
input  wire          mplla_oword_clk,
input  wire          mplla_div66_clk,
input  wire          mplla_div33_clk,
input  wire          mplla_div16p5_clk,
input  wire          mplla_div_clk,

// MPLLB clocks
input  wire          mpllb_word_clk,
input  wire          mpllb_dword_clk,
input  wire          mpllb_qword_clk,
input  wire          mpllb_oword_clk,
input  wire          mpllb_div_clk,

// Lane interface
output wire          lane_tx2rx_ser_lb_en,
output wire          lane_rx2tx_par_lb_en,

// Transmit interface
output wire          tx_clk,
output wire          tx_clk_rdy,
output wire [19:0]   tx_data,
output wire          tx_data_en,
output wire          tx_invert,
output wire          tx_reset,
output wire          tx_req,
output wire [1:0]    tx_pstate,
output wire          tx_lpd,
output wire [1:0]    tx_width,
output wire [2:0]    tx_rate,
output wire          tx_mpllb_sel,
output wire          tx_vboost_en,
output wire [3:0]    tx_iboost_lvl,
output wire          tx_detrx_req,
input  wire          tx_ack,
input  wire          tx_detrx_result,

// Receive interface
input  wire          rx_clk,
output wire          rx_reset,
output wire          rx_req,
output wire [1:0]    rx_rate,
output wire [1:0]    rx_width,
output wire [1:0]    rx_pstate,
output wire          rx_lpd,
output wire [5:0]    rx_ref_ld_val,
output wire [12:0]   rx_vco_ld_val,
output wire          rx_cdr_vco_lowfreq,
output wire          rx_adapt_afe_en,
output wire          rx_adapt_dfe_en,
output wire [2:0]    rx_eq_att_lvl,
output wire [3:0]    rx_eq_vga1_gain,
output wire [3:0]    rx_eq_vga2_gain,
output wire [2:0]    rx_eq_ctle_pole,
output wire [4:0]    rx_eq_ctle_boost,
output wire [7:0]    rx_eq_dfe_tap1,
output wire [6:0]    rx_eq_dfe_tap2,
output wire [6:0]    rx_eq_dfe_tap3,
output wire [6:0]    rx_eq_dfe_tap4,
output wire [6:0]    rx_eq_dfe_tap5,
output wire          rx_data_en,
output wire          rx_cdr_track_en,
output wire [2:0]    rx_los_threshold,
input  wire          rx_ack,
input  wire          rx_los,
input  wire          rx_valid,
input  wire [1:0]    rx_adapt_sts,

// -----------------------------------------------
// PHY SIDE XFACE
// -----------------------------------------------

// Internal from/to other Raw PCS lanes (pcs_raw_lane)
output wire          lane_mplla_en_in_i,
output wire          lane_mpllb_en_in_i,
input  wire          lane_mplla_en_out_i,
input  wire          lane_mpllb_en_out_i,

// SUP interface
output wire          mplla_en_i,
output wire          mpllb_en_i,
output wire          mplla_state_i,
output wire          mpllb_state_i,

// MPLLA clocks
output wire          mplla_word_clk_i,
output wire          mplla_dword_clk_i,
output wire          mplla_qword_clk_i,
output wire          mplla_oword_clk_i,
output wire          mplla_div66_clk_i,
output wire          mplla_div33_clk_i,
output wire          mplla_div16p5_clk_i,
output wire          mplla_div_clk_i,

// MPLLB clocks
output  wire         mpllb_word_clk_i,
output  wire         mpllb_dword_clk_i,
output  wire         mpllb_qword_clk_i,
output  wire         mpllb_oword_clk_i,
output  wire         mpllb_div_clk_i,

// Common interface
input  wire          mplla_init_cal_disable_i,
input  wire          mpllb_init_cal_disable_i,

// Lane interface
input  wire          lane_tx2rx_ser_lb_en_i,
input  wire          lane_rx2tx_par_lb_en_i,

// Transmit interface
input  wire          tx_clk_i,
input  wire          tx_clk_rdy_i,
input  wire [19:0]   tx_data_i,
input  wire          tx_data_en_i,
input  wire          tx_invert_i,
input  wire          tx_reset_i,
input  wire          tx_req_i,
input  wire [1:0]    tx_pstate_i,
input  wire          tx_lpd_i,
input  wire [1:0]    tx_width_i,
input  wire [2:0]    tx_rate_i,
input  wire          tx_mpllb_sel_i,
input  wire          tx_vboost_en_i,
input  wire [3:0]    tx_iboost_lvl_i,
input  wire          tx_detrx_req_i,
output wire          tx_ack_i,
output wire          tx_detrx_result_i,

// Receive interface
output  wire         rx_clk_i,
input   wire         rx_reset_i,
input   wire         rx_req_i,
input   wire [1:0]   rx_rate_i,
input   wire [1:0]   rx_width_i,
input   wire [1:0]   rx_pstate_i,
input   wire         rx_lpd_i,
input   wire [5:0]   rx_ref_ld_val_i,
input   wire [12:0]  rx_vco_ld_val_i,
input   wire         rx_cdr_vco_lowfreq_i,
input   wire         rx_adapt_afe_en_i,
input   wire         rx_adapt_dfe_en_i,
input   wire [2:0]   rx_eq_att_lvl_i,
input   wire [3:0]   rx_eq_vga1_gain_i,
input   wire [3:0]   rx_eq_vga2_gain_i,
input   wire [2:0]   rx_eq_ctle_pole_i,
input   wire [4:0]   rx_eq_ctle_boost_i,
input   wire [7:0]   rx_eq_dfe_tap1_i,
input   wire [6:0]   rx_eq_dfe_tap2_i,
input   wire [6:0]   rx_eq_dfe_tap3_i,
input   wire [6:0]   rx_eq_dfe_tap4_i,
input   wire [6:0]   rx_eq_dfe_tap5_i,
input   wire         rx_data_en_i,
input   wire         rx_cdr_track_en_i,
input   wire [2:0]   rx_los_threshold_i,
output  wire         rx_ack_i,
output  wire         rx_los_i,
output  wire         rx_valid_i,
output  wire [1:0]   rx_adapt_sts_i,

// Control Register Bus
//
input  wire                       cr_clk,
input  wire                       cr_rst,
input  wire                       cr_wr_en,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_wr_data,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_rd_data,
input  wire [8:0]                 cr_sel
);

// %%CREG LANE_OVRD_IN - Override values for incoming LANE controls
//   OFFSET: 0x0
//   ATTR:   RW, CUST
//   FIELDS:
//      [2] LANE_OVRD_EN         - Override enable for signals in this register
//          RESET: 0x0
//      [1] LANE_MPLLB_EN_IN     - Override value for lane_mpllb_en_in
//          RESET: 0x1
//      [0] LANE_MPLLA_EN_IN     - Override value for lane_mplla_en_in
//          RESET: 0x1
//
wire        lane_ovrd_in_en;
wire        lane_mpllb_en_in_r;
wire        lane_mplla_en_in_r;
wire        cr_sel_lane_ovrd_in = cr_sel[0];
wire [15:0] cr_lane_ovrd_in_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(3), .RST_VAL(3'b0_1_1), .MSK_VAL(3'd0))
  lane_ovrd_in_reg (
    .cr_val({
             lane_ovrd_in_en,
             lane_mpllb_en_in_r,
             lane_mplla_en_in_r
             }),
    .cr_rd_data(cr_lane_ovrd_in_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_lane_ovrd_in),
    .cr_self_clr (1'b0)
);

// %%CREG LANE_OVRD_OUT - Override values for outgoing LANE controls
//   OFFSET: 0x1
//   ATTR:   RW, CUST
//   FIELDS:
//      [2] LANE_OVRD_EN         - Override enable for signals in this register
//          RESET: 0x0
//      [1] LANE_MPLLB_EN_OUT    - Override value for lane_mpllb_en_out
//          RESET: 0x1
//      [0] LANE_MPLLA_EN_OUT    - Override value for lane_mplla_en_out
//          RESET: 0x1
//
wire        lane_ovrd_out_en;
wire        lane_mpllb_en_out_r;
wire        lane_mplla_en_out_r;
wire        cr_sel_lane_ovrd_out = cr_sel[1];
wire [15:0] cr_lane_ovrd_out_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(3), .RST_VAL(3'b0_1_1), .MSK_VAL(3'd0))
  lane_ovrd_out_reg (
    .cr_val({
             lane_ovrd_out_en,
             lane_mpllb_en_out_r,
             lane_mplla_en_out_r
             }),
    .cr_rd_data(cr_lane_ovrd_out_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_lane_ovrd_out),
    .cr_self_clr (1'b0)
);

// %%CREG SUP_OVRD_IN - Override values for incoming SUP controls from PMA
//   OFFSET: 0x2
//   ATTR:   RW, CUST
//   FIELDS:
//      [2] SUP_STATE_OVRD_EN    - Override enable for signals in this register
//          RESET: 0x0
//      [1] MPLLB_STATE          - Override value for mpllb_state
//          RESET: 0x0
//      [0] MPLLA_STATE          - Override value for mplla_state
//          RESET: 0x0
//
wire        sup_ovrd_in_en;
wire        mpllb_state_r;
wire        mplla_state_r;
wire        cr_sel_sup_ovrd_in = cr_sel[2];
wire [15:0] cr_sup_ovrd_in_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(3), .RST_VAL(3'b0_0_0), .MSK_VAL(3'd0))
  sup_ovrd_in_reg (
    .cr_val({
             sup_ovrd_in_en,
             mpllb_state_r,
             mplla_state_r
             }),
    .cr_rd_data(cr_sup_ovrd_in_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_sup_ovrd_in),
    .cr_self_clr (1'b0)
);

// %%CREG SUP_PMA_IN - Current values for coming SUP status controls from PMA
//   OFFSET: 0x3
//   ATTR: READ, VOL, CUST
//   FIELDS:
//      [2] RTUNE_ACK   - Value from PMA for rtune_ack
//      [1] MPLLB_STATE - Value from PMA for mpllb_state
//      [0] MPLLA_STATE - Value from PMA for mplla_state
//
wire        cr_sel_sup_pma_in = cr_sel[3];
wire [15:0] cr_sup_pma_in_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(3))
  sup_pma_in_reg (
    .cr_val({
             rtune_ack,
             (mpllb_state | mpllb_init_cal_disable_i),
             (mplla_state | mplla_init_cal_disable_i)
             }),
    .cr_rd_data(cr_sup_pma_in_rd_data),
    .cr_sel(cr_sel_sup_pma_in)
);

// %%CREG TX_OVRD_OUT - Override values for outgoing TX controls to PMA
//   OFFSET: 0x4
//   ATTR:   RW, CUST
//   FIELDS:
//      [3] TX_RESET_OVRD_EN  - Override enable for tx_reset
//          RESET: 0x0
//      [2] TX_RESET_OVRD_VAL - Override value for tx_reset
//          RESET: 0x0
//      [1] TX_REQ_OVRD_EN    - Override enable for tx_req
//          RESET: 0x0
//      [0] TX_REQ_OVRD_VAL   - Override value for tx_req
//          RESET: 0x0
//
wire        tx_reset_ovrd_en;
wire        tx_reset_r;
wire        tx_req_ovrd_en;
wire        tx_req_r;
wire        cr_sel_tx_ovrd_out = cr_sel[4];
wire [15:0] cr_tx_ovrd_out_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(4), .RST_VAL(4'b0_0_0_0), .MSK_VAL(4'd0))
  tx_ovrd_out_reg (
    .cr_val({
             tx_reset_ovrd_en,
             tx_reset_r,
             tx_req_ovrd_en,
             tx_req_r
             }),
    .cr_rd_data(cr_tx_ovrd_out_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_tx_ovrd_out),
    .cr_self_clr (1'b0)
);

// %%CREG TX_PMA_IN - Current values for coming TX status controls from PMA
//   OFFSET: 0x5
//   ATTR: READ, VOL, CUST
//   FIELDS:
//      [0] ACK         - Value from PMA for tx_ack
//
wire        cr_sel_tx_pma_in = cr_sel[5];
wire [15:0] cr_tx_pma_in_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(1))
  tx_pma_in_reg (
    .cr_val({
             tx_ack_i
             }),
    .cr_rd_data(cr_tx_pma_in_rd_data),
    .cr_sel(cr_sel_tx_pma_in)
);

// %%CREG RX_OVRD_OUT - Override values for outgoing RX controls to PMA
//   OFFSET: 0x6
//   ATTR:   RW, CUST
//   FIELDS:
//      [3] RX_RESET_OVRD_EN  - Override enable for rx_reset
//          RESET: 0x0
//      [2] RX_RESET_OVRD_VAL - Override value for rx_reset
//          RESET: 0x0
//      [1] RX_REQ_OVRD_EN    - Override enable for rx_req
//          RESET: 0x0
//      [0] RX_REQ_OVRD_VAL   - Override value for rx_req
//          RESET: 0x0
//
wire        rx_reset_ovrd_en;
wire        rx_reset_r;
wire        rx_req_ovrd_en;
wire        rx_req_r;
wire        cr_sel_rx_ovrd_out = cr_sel[6];
wire [15:0] cr_rx_ovrd_out_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(4), .RST_VAL(4'b0_0_0_0), .MSK_VAL(4'd0))
  rx_ovrd_out_reg (
    .cr_val({
             rx_reset_ovrd_en,
             rx_reset_r,
             rx_req_ovrd_en,
             rx_req_r
             }),
    .cr_rd_data(cr_rx_ovrd_out_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_rx_ovrd_out),
    .cr_self_clr (1'b0)
);

// %%CREG RX_PMA_IN - Current values for coming RX status controls from PMA
//   OFFSET: 0x7
//   ATTR: READ, VOL, CUST
//   FIELDS:
//      [0] ACK         - Value from PMA for rx_ack
//
wire        cr_sel_rx_pma_in = cr_sel[7];
wire [15:0] cr_rx_pma_in_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(1))
  rx_pma_in_reg (
    .cr_val({
             rx_ack_i
             }),
    .cr_rd_data(cr_rx_pma_in_rd_data),
    .cr_sel(cr_sel_rx_pma_in)
);

// %%CREG LANE_RTUNE_CTL - Lane Rtune Controls
//   OFFSET: 0x8
//   ATTR:   RW, CUST
//   FIELDS:
//      [0] LANE_RTUNE_REQ      - Lane value for rtune_req
//          RESET: 0x0
//
wire        lane_rtune_req_r;
wire        cr_sel_lane_rtune_ctl = cr_sel[8];
wire [15:0] cr_lane_rtune_ctl_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(1), .RST_VAL(1'b0), .MSK_VAL(1'd0))
  lane_rtune_ctl_reg (
    .cr_val({
             lane_rtune_req_r
             }),
    .cr_rd_data(cr_lane_rtune_ctl_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst),
    .cr_sel(cr_sel_lane_rtune_ctl),
    .cr_self_clr (1'b0)
);

// Generate final control register read data for this module
//
assign cr_rd_data = (
                     cr_lane_ovrd_in_rd_data  |
                     cr_lane_ovrd_out_rd_data |
                     cr_sup_ovrd_in_rd_data   |
                     cr_sup_pma_in_rd_data    |
                     cr_tx_ovrd_out_rd_data   |
                     cr_tx_pma_in_rd_data     |
                     cr_rx_ovrd_out_rd_data   |
                     cr_rx_pma_in_rd_data     |
                     cr_lane_rtune_ctl_rd_data
                    );


////////////////////
// Inputs
////////////////////
// LANE inputs
dwc_e12mp_phy_x4_ns_asic_in lane_mplla_en_in_in (
  .asic           (lane_mplla_en_in),
  .phy            (lane_mplla_en_in_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (lane_ovrd_in_en),
  .cr_ovrd_val    (lane_mplla_en_in_r & ~mplla_init_cal_disable_i)
);
dwc_e12mp_phy_x4_ns_asic_in lane_mpllb_en_in_in (
  .asic           (lane_mpllb_en_in),
  .phy            (lane_mpllb_en_in_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (lane_ovrd_in_en),
  .cr_ovrd_val    (lane_mpllb_en_in_r & ~mpllb_init_cal_disable_i)
);

// SUP inputs
assign mplla_en_i = mplla_en;
assign mpllb_en_i = mpllb_en;
dwc_e12mp_phy_x4_ns_asic_in mplla_state_in (
  .asic           (mplla_state),
  .phy            (mplla_state_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (sup_ovrd_in_en),
  .cr_ovrd_val    (mplla_state_r)
);
dwc_e12mp_phy_x4_ns_asic_in mpllb_state_in (
  .asic           (mpllb_state),
  .phy            (mpllb_state_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (sup_ovrd_in_en),
  .cr_ovrd_val    (mpllb_state_r)
);
assign mplla_word_clk_i    = mplla_word_clk;
assign mplla_dword_clk_i   = mplla_dword_clk;
assign mplla_qword_clk_i   = mplla_qword_clk;
assign mplla_oword_clk_i   = mplla_oword_clk;
assign mplla_div66_clk_i   = mplla_div66_clk;
assign mplla_div33_clk_i   = mplla_div33_clk;
assign mplla_div16p5_clk_i = mplla_div16p5_clk;
assign mplla_div_clk_i     = mplla_div_clk;
assign mpllb_word_clk_i    = mpllb_word_clk;
assign mpllb_dword_clk_i   = mpllb_dword_clk;
assign mpllb_qword_clk_i   = mpllb_qword_clk;
assign mpllb_oword_clk_i   = mpllb_oword_clk;
assign mpllb_div_clk_i     = mpllb_div_clk;

assign rx_clk_i         = rx_clk;
assign tx_ack_i         = tx_ack;
assign tx_detrx_result_i= tx_detrx_result;
assign rx_ack_i         = rx_ack;
assign rx_los_i         = lane_tx2rx_ser_lb_en ? ~tx_data_en : rx_los; // Mantis 5903
assign rx_valid_i       = rx_valid;
assign rx_adapt_sts_i   = rx_adapt_sts;


////////////////////
// Outputs
////////////////////

// LANE
dwc_e12mp_phy_x4_ns_asic_out lane_mplla_en_out_out (
  .asic           (lane_mplla_en_out),
  .phy            (lane_mplla_en_out_i),
  .cr_ovrd        (lane_ovrd_out_en),
  .cr_ovrd_val    (lane_mplla_en_out_r)
);
dwc_e12mp_phy_x4_ns_asic_out lane_mpllb_en_out_out (
  .asic           (lane_mpllb_en_out),
  .phy            (lane_mpllb_en_out_i),
  .cr_ovrd        (lane_ovrd_out_en),
  .cr_ovrd_val    (lane_mpllb_en_out_r)
);

// Mantis 6264
// Need to aggregate rtune request from lanes
assign lane_rtune_req_out  = lane_rtune_req_r | lane_rtune_req_in;

assign lane_tx2rx_ser_lb_en = lane_tx2rx_ser_lb_en_i;
assign lane_rx2tx_par_lb_en = lane_rx2tx_par_lb_en_i;
// TX
// Invert tx_clk for pma when ANI_SIM_GATES is defined
`ifdef ANI_SIM_GATES
assign tx_clk = ~tx_clk_i;
`else
assign tx_clk = tx_clk_i;
`endif
assign tx_clk_rdy = tx_clk_rdy_i;
assign tx_data    = tx_data_i;
assign tx_data_en = tx_data_en_i;
assign tx_invert  = tx_invert_i;
dwc_e12mp_phy_x4_ns_asic_out tx_reset_out (
  .asic           (tx_reset),
  .phy            (tx_reset_i),
  .cr_ovrd        (tx_reset_ovrd_en),
  .cr_ovrd_val    (tx_reset_r)
);
dwc_e12mp_phy_x4_ns_asic_out tx_req_out (
  .asic           (tx_req),
  .phy            (tx_req_i),
  .cr_ovrd        (tx_req_ovrd_en),
  .cr_ovrd_val    (tx_req_r)
);
assign tx_pstate     = tx_pstate_i;
assign tx_lpd        = tx_lpd_i;
assign tx_width      = tx_width_i;
assign tx_rate       = tx_rate_i;
assign tx_mpllb_sel  = tx_mpllb_sel_i;
assign tx_vboost_en  = tx_vboost_en_i;
assign tx_iboost_lvl = tx_iboost_lvl_i;
assign tx_detrx_req  = tx_detrx_req_i;

// RX
dwc_e12mp_phy_x4_ns_asic_out rx_reset_out (
  .asic           (rx_reset),
  .phy            (rx_reset_i),
  .cr_ovrd        (rx_reset_ovrd_en),
  .cr_ovrd_val    (rx_reset_r)
);
dwc_e12mp_phy_x4_ns_asic_out rx_req_out (
  .asic           (rx_req),
  .phy            (rx_req_i),
  .cr_ovrd        (rx_req_ovrd_en),
  .cr_ovrd_val    (rx_req_r)
);
assign rx_rate            = rx_rate_i;
assign rx_width           = rx_width_i;
assign rx_pstate          = rx_pstate_i;
assign rx_lpd             = rx_lpd_i;
assign rx_ref_ld_val      = rx_ref_ld_val_i;
assign rx_vco_ld_val      = rx_vco_ld_val_i;
assign rx_cdr_vco_lowfreq = rx_cdr_vco_lowfreq_i;
assign rx_adapt_afe_en    = rx_adapt_afe_en_i;
assign rx_adapt_dfe_en    = rx_adapt_dfe_en_i;
assign rx_eq_att_lvl      = rx_eq_att_lvl_i;
assign rx_eq_vga1_gain    = rx_eq_vga1_gain_i;
assign rx_eq_vga2_gain    = rx_eq_vga2_gain_i;
assign rx_eq_ctle_pole    = rx_eq_ctle_pole_i;
assign rx_eq_ctle_boost   = rx_eq_ctle_boost_i;
assign rx_eq_dfe_tap1     = rx_eq_dfe_tap1_i;
assign rx_eq_dfe_tap2     = rx_eq_dfe_tap2_i;
assign rx_eq_dfe_tap3     = rx_eq_dfe_tap3_i;
assign rx_eq_dfe_tap4     = rx_eq_dfe_tap4_i;
assign rx_eq_dfe_tap5     = rx_eq_dfe_tap5_i;
assign rx_data_en         = rx_data_en_i;
assign rx_cdr_track_en    = rx_cdr_track_en_i;
assign rx_los_threshold   = rx_los_threshold_i;

endmodule

